The increasing pervasiveness of the Internet is straining information technology manufacturer's and service provider's capabilities to meet market demands for increasingly higher bandwidth, processor intensive services. Great advances have been implemented in the delivery networks, for example backbone capacities and intra-network delivery capacities. Intensive research efforts promise to continue the advances in network delivery capabilities. The widespread implementation of fiber optic carriers is one example of the industry response to increasing demands placed on the current information system infrastructures.
Improvements in semiconductor manufacture techniques are providing advances in microprocessor computational capabilities on par with the technological progress being made in delivery networks. The well known Moore's law succinctly summarizes the commercial pressure processor manufactures labor under.
The Internet, and the massive data infrastructures being propagated thereby, is producing an increasing reliance on distributed and parallel processing capabilities. While the processing and delivery capabilities of the carrier networks are, in general, satisfying current demands, a specific technological area that appears to be lagging in performance requirements is the input/output (I/O) capabilities of these distributed systems. Typical performance bottlenecks are often unrelated to the transport network capacities and processor node capacities but rather relate to the input/output systems. Shared bus input/output systems common in today's information technology infrastructures are often overwhelmed by the demands placed on them.
Recently the deficiencies of current input/output devices and standards have become the focus of research and development by a number of corporations. The dramatic performance increases recently observed in backbone networks, for example T3 and OC3, and transport network infrastructures have been notably diverging from advances in local network capabilities, for example Ethernet. Likewise, advances in system level interfacing technologies, for example SCSI, are lagging behind progress of transport capacities.
Various standards have been introduced, with varying levels of market acceptance, over the years to improve system interfacing and input/output performance. One of the more successful peripheral interconnection standards is the peripheral component interconnect (PCI) standard introduced by Intel. PCI proved far superior than the previous common standard, the VESA local bus. However, with backbones currently surpassing GB/s transmissions, systems interfacing thereto are failing to adequately handle these high bandwidths resulting in input/output bottlenecks at processing nodes receiving information therefrom. Consequently, data intensive systems, for example Internet servers providing information services to massive numbers of users, are becoming increasingly distributed and require further sophistication of the input/output systems.
Shared bus technologies effectively address input/output requirements for standalone computing and networking on a limited basis. However, the plethora of interfacing on typical PCs in networking environments strains the capabilities of common bus technologies. Clearly, the scale of networking found today was not considered when many of the common bussing architectures were being developed. Furthermore, as new standards are implemented to exploit the increasingly efficient transport networks, system scalability becomes even more complex. Increasing scalability often results in a corresponding decrease in bus performance because the efficiency of shared bus technologies decreases in proportion to the number of devices supported thereby.
Typical switching systems for interfacing various communication protocol mediums employ a backplane with add on cards for each I/O channel. In relatively small switching systems, for example eight port switching systems, the cost of the printed circuit boards can be a significant percentage of the total switch cost. Furthermore, as the demands for improved performance increase and the overall scalability of information systems increases, the demand for increased system miniaturization likewise increases. Configuring numerous ports around a central switching fabric presents numerous challenges in itself. For instance, signal traces need to be kept to a minimum length to preserve signal integrity and device-to-device timing. Furthermore, most chassis' are designed for all peripheral connections to be made on a common plane. Thus, having ports on two or more sides of the switching fabric is typically undesirable.
Therefore, it may be seen from the foregoing that a solution for providing a reduction in the overall size and the number of printed circuit boards required in a switched I/O system is desired.